The present invention relates to an output driver for outputting data or signals to the outside of a chip in a semiconductor device, and more particularly to an output driver that is capable of meeting a variety of interface standards.
In semiconductor devices, an output driver is used to output stored data or operation results to the outside of a chip. Semiconductor devices may be applied to a variety of systems, each of which may have different interface standards. For example, a dynamic random access memory (DRAM), which is one type of semiconductor memory device, may be applied to a system that uses a Pseudo Open Drain (POD) interface standard, or a system that uses a Low Voltage CMOS (LVCMOS) interface standard. The POD interface and the LVCOS interface are defined in the JEDEC standard.
In this case, the semiconductor memory devices use two types of output drivers, which will be described below.
FIG. 1 is a block diagram of an output driver that is applicable to a POD interface standard.
The output driver using the POD interface includes a pre-driver 110, a pull-up driver 120, and a pull-down driver 130. The output driver further includes a termination resistor unit 140 at an input/output pad DQ for data input.
The pre-driver 110 controls the pull-up driver 120 and the pull-down driver 130 to output data DATA. The pre-driver 110 enables the pull-up driver 120 when the data DATA to be output is logic high data, and enables the pull-down driver 130 when the data DATA to be output is logic low data. In addition, the pre-driver 110 determines resistances the pull-up driver 120 and the pull-down driver 130 will have when they are enabled. In FIG. 1, reference symbol “OUTEN” represents an enable signal of the output driver, reference symbol “DS” (driver strength) represents information on target resistance the drivers 120 and 130 must have, and reference symbol “LVCMOS” represents a signal discriminating an LVCMOS mode and a POD mode. When activated, the signal indicates the LVCMOS mode; and when deactivated, the signal indicates the POD mode.
The pull-up driver 120 includes a number of resistors connected in parallel. The pull-up driver 120 is enabled to terminate the output pad DQ to a pull-up voltage level and outputs the logic high data. Whether to enable the pull-up driver 120 and which resistor of the parallel resistors is to be turned on are determined under the control of the pre-driver 110.
The pull-down driver 130 includes a number of resistors connected in parallel. The pull-down driver 130 is enabled to terminate the output node DQ to a pull-down voltage level and outputs the logic low data. Whether to enable the pull-down driver 130 and which resistor of the parallel resistors is to be turned on are determined under the control of the pre-driver 110.
Upon receipt of data on the basis of the POD interface standard, the termination resistor unit 140 is turned on to terminate the input/output pad DQ. The termination resistor unit 140 is related to only the data input, and it is not the element of the output driver. When data is received on the basis of the POD interface standard, the termination resistor unit 140 is turned on and data is input with an adjusted swing width. This portion is not shown in the drawing. Since the pull-up driver 120 can function to terminate the input/output pad DQ, it may perform the function of the termination resistor unit 140 at the same time according to systems to which the output driver is applied.
FIG. 2 is a circuit diagram of the pull-up driver 120 of FIG. 1.
Referring to FIG. 2, the pull-up driver 120 includes a number of parallel resistors that are turned on/off in response to output signals A, B, C and D of the pre-driver 110.
When the signals A, B, C and D are all activated to a low level, a total resistance of the parallel resistors (240Ω, 240Ω, 120Ω, 60Ω) is equal to 30Ω. As a result, the pull-up driver 120 meets the target resistance of 30Ω. If the target resistance is 40Ω, only the signals A and B are activated and the pull-up driver 120 meets the target resistance. Also, the pull-up driver 120 meets the target resistance of 50Ω when the signals A and C are activated.
Like the pull-up driver 120, the pull-down driver 130 may include a plurality of parallel resistors. However, in contrast to the pull-up driver 120, the pull-down driver 130 is implemented with NMOS transistors as the parallel resistors.
FIG. 3 is a circuit diagram of the pre-driver 110 of FIG. 1.
The structure for controlling the pull-up driver 120 is illustrated in FIG. 3, while the structure for controlling the pull-down driver 130 is omitted. Although not illustrated, the circuit of the pre-driver 110 for controlling the pull-down driver 130 may be configured with the same structure as that shown in FIG. 3, except that logic states of several signals are opposite to those in FIG. 3.
The pre-driver 110 operates when the enable signal OUTEN is activated and the signal LVCMOS is deactivated, that is, in the POD mode. Reference numerals 30, 40 and 50 represent signals that are activated when the target resistance is 30Ω, 40Ω and 50Ω, respectively. These signals 30, 40 and 50 are denoted by the reference symbol “DS” in FIG. 1.
The pre-driver 110 activates the signals A, B, C and D when data to be output is logic high data and the target resistance is 30Ω, and activates the signals A and B when data to be output is logic high data and the target resistance is 40Ω. Also, the pre-driver 110 activates the signals A and C when data to be output is logic high data and the target resistance is 50Ω.
Using RC delays of resistors and capacitors provided at output terminals of the signals A, B, C and D, slew rates of the signals A, B, C and D driving the pull-up driver 120 are adjusted to meet the POD interface standard.
FIG. 4 is a block diagram of an output driver that is applicable to an LVCMOS interface standard.
The output driver using the LVCMOS includes a pre-driver 410 and a pull-down driver 430. The output driver does not include a termination resistor unit 140 of FIG. 1 even upon data input.
The pre-driver 410 controls the pull-up driver 420 and the pull-down driver 430 to output data DATA. The pre-driver 410 enables the pull-up driver 420 when the data DATA to be output is logic high data, and enables the pull-down driver 430 when the data DATA to be output is logic low data. In addition, the pre-driver 410 determines resistances the pull-up driver 420 and the pull-down driver 430 will have when they are enabled. In FIG. 4, a reference symbol “OUTEN” represents an enable signal of the output driver, a reference symbol “DS” (driver strength) represents information on target resistance the drivers 420 and 430 must have, and a reference symbol “LVCMOS” represents a signal discriminating an LVCMOS mode and a POD mode. When activated, the signal indicates the LVCMOS mode; and when deactivated, the signal indicates the POD mode.
The pull-up driver 420 includes a plurality of resistors connected in parallel. The pull-up driver 420 is enabled to terminate the output pad DQ to a pull-up voltage level and outputs the logic high level data. Whether to enable the pull-up driver 420 and which resistor of the parallel resistors is to be turned on are determined under the control of the pre-driver 410.
The pull-down driver 430 includes a plurality of resistors connected in parallel. The pull-down driver 430 is enabled to terminate the output node DQ to a pull-down voltage level and outputs the logic low level data. Whether to enable the pull-down driver 430 and which resistor of the parallel resistors is to be turned on are determined under the control of the pre-driver 410.
FIG. 5 is a circuit diagram of the pull-up driver 420 of FIG. 1.
Referring to FIG. 5, the pull-up driver 420 includes a plurality of parallel resistors that are turned on/off in response to output signals E and F of the pre-driver 410.
When the signals E and F are activated to a low level, a total resistance of the parallel resistors (60Ω, 60Ω) is equal to 30Ω. As a result, the pull-up driver 420 meets the target resistance of 30Ω. The pull-up driver 420 meets the target resistance of 60Ω when the signal E is activated.
Like the pull-up driver 420, the pull-down driver 430 may include a plurality of parallel resistors. However, the parallel resistors of the pull-down driver 430 are implemented with NMOS transistors, as opposed to the pull-up driver 420.
FIG. 6 is a circuit diagram of the pre-driver 410 of FIG. 4.
A part for controlling the pull-up driver 420 is illustrated in FIG. 3, while a part for controlling the pull-down driver 430 is omitted. Although not illustrated, the circuit of the pre-driver 410 for controlling the pull-down driver 430 may be configured in the same structure as that of FIG. 6, except that logic states of several signals are opposite to those of FIG. 6.
The pre-driver 410 operates when the enable signal OUTEN is activated and the signal LVCMOS is activated, that is, in the LVCMOS mode. A reference numeral 30 represents a signal that is activated when the target resistance is 30Ω. This signal is denoted by the reference symbol “DS” in FIG. 4.
The pre-driver 410 activates the signals E and F when data to be output is logic high data and the target resistance is 30Ω, and activates the signal E when data to be output is logic high data and the target resistance is 60Ω.
Using RC delays of resistors and capacitors provided at output terminals of the signals E and F, slew rates of the signals E and F driving the pull-up driver 420 are adjusted to meet the LVCMOS interface standard.
The conventional semiconductor memory device applicable to the POD interface standard and the LVCMOS interface standard includes the output drivers of FIGS. 1 and 4 at the data output terminal DQ in order to meet two types of interface standards each of which has a different target resistance and slew rate. In this case, the circuit area of the semiconductor memory device increases, and such a structure is problematic in the trends that the number of I/O pins (DQ pins) gradually increases.